UNIVERSAL TEST SET GENERATION FOR CMOS CIRCUITS

被引:0
|
作者
CHEN, BY [1 ]
LEE, CL [1 ]
机构
[1] NATL CHIAO TUNG UNIV,INST ELECTR,HSINCHU 30050,TAIWAN
来源
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 1995年 / 6卷 / 03期
关键词
AUTOMATIC TESTING GENERATION; CMOS CIRCUITS; FUNCTIONAL TESTING; UNIVERSAL TEST SET; STUCK-OPEN FAULTS;
D O I
10.1007/BF00996439
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Based on the unate function theory, a universal test set for CMOS stuck-open faults in a functional block has been proposed in the existing literature. Thus, it is known that tests can be generated from the functional description and can detect all detectable stuck-open faults in any ''restricted CMOS circuit'' implementation of the function. However, the procedure to generate the tests involves a process of enumerating the expanded truth table of the function and comparing the vectors in the table. This is a very computationally demanding process. In this paper, a fast algorithm to generate the universal test set for CMOS circuits is presented. The algorithm generates the tests directly by Shannon-expanding and complementing the function, instead of the truth table enumerating. This greatly reduces the time complexity and the requirement of temporary memory. Besides, the algorithm represents the tests by ''cubes'' instead of the conventional ''patterns''. This also reduces the memory requirement for test-storing. Experimental results show that the algorithm achieves an improvement of up to six orders of magnitude in the computational efficiency and a saving of up to 2000-fold in the memory requirement for storing the tests when compared to other methods.
引用
收藏
页码:313 / 323
页数:11
相关论文
共 50 条
  • [21] Estimating power consumption of CMOS circuits modelled as symbolic neural networks
    Macii, E
    Poncino, M
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1996, 143 (05): : 331 - 336
  • [22] Nonstuck behaviour of open circuit supply faults in CMOS logic circuits
    Johnson, S
    Morant, MJ
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1996, 143 (01): : 9 - 13
  • [23] Analysis and design of PTAT temperature sensor in digital CMOS VLSI circuits
    Golda, A.
    Kos, A.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, : 415 - +
  • [24] Maximum power estimation for CMOS circuits using deterministic and statistical approaches
    Wang, CY
    Roy, K
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1998, 6 (01) : 134 - 140
  • [25] A Method for Finding Multiple DC Operating Points of Short Channel CMOS Circuits
    Tadeusiewicz, Michal
    Halgas, Stanislaw
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2013, 32 (05) : 2457 - 2468
  • [26] Quaternary voltage-mode CMOS circuits for multiple-valued logic
    Thoidis, I
    Soudris, D
    Karafyllidis, I
    Christoforidis, S
    Thanailakis, A
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1998, 145 (02): : 71 - 77
  • [27] Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits
    Elgharbawy, Walid M.
    Golconda, Pradeep
    Moursy, Abdelhamid G.
    Bayoumi, Magdy A.
    JOURNAL OF LOW POWER ELECTRONICS, 2007, 3 (02) : 175 - 188
  • [28] Characterization of 4 KCMOS devices and circuits for hybrid Josephson-CMOS systems
    Yoshikawa, N
    Tomida, T
    Tokuda, A
    Liu, Q
    Meng, X
    Whiteley, SR
    Van Duzer, T
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2005, 15 (02) : 267 - 271
  • [29] A Method for Finding Multiple DC Operating Points of Short Channel CMOS Circuits
    Michał Tadeusiewicz
    Stanisław Hałgas
    Circuits, Systems, and Signal Processing, 2013, 32 : 2457 - 2468
  • [30] Low-voltage subthreshold CMOS current mode circuits: Design and applications
    Eldeeb, Mohammed A.
    Ghallab, Yehya H.
    Ismail, Yehea
    Elghitani, Hassan
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2017, 82 : 251 - 264