MICROPROGRAMMABLE PIPELINED VECTOR PROCESSOR

被引：0

作者：

MADESWARAN, V ^{[1
]}

MATHIALAGAN, A ^{[1
]}

机构：

[1] ANNA UNIV,MADRAS INST TECHNOL,MADRAS 600025,INDIA

来源：

COMPUTERS IN INDUSTRY | 1990年 / 13卷 / 04期

关键词：

Branch predictor; Interleaved memory; Microprogramming; Pipelining; Vector computation;

D O I：

10.1016/0166-3615(90)90009-E

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

The design goal of the machine is process enhancement for vector computations through a low-level parallel processing organization. Continuous streaming of data from the high-bandwidth interleaved memory to the functional unit and the memory-to-memory pipeline operation make long vector processes efficient. The hazards of pipelines caused by unconditional branch instructions are avoided by a branch predictor. The various components are independently controlled by different fields of a 40-bit horizontal type microinstruction. The user can tailor the architecture to the application at hand through the use of the writtable control storage. © 1990.

引用

页码：367 / 370

页数：4

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