MICROPROGRAMMABLE PIPELINED VECTOR PROCESSOR

The design goal of the machine is process enhancement for vector computations through a low-level parallel processing organization. Continuous streaming of data from the high-bandwidth interleaved memory to the functional unit and the memory-to-memory pipeline operation make long vector processes efficient. The hazards of pipelines caused by unconditional branch instructions are avoided by a branch predictor. The various components are independently controlled by different fields of a 40-bit horizontal type microinstruction. The user can tailor the architecture to the application at hand through the use of the writtable control storage. © 1990.