A NEW LINEAR SYSTOLIC ARRAY FOR FFT COMPUTATION

被引：14

作者：

CHOI, JY ^{[1
]}

BORIAKOFF, V ^{[1
]}

机构：

[1] WORCESTER POLYTECH INST,DEPT ELECT ENGN,WORCESTER,MA 01609

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1992年 / 39卷 / 04期

关键词：

D O I：

10.1109/82.136573

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a new linear systolic array for FFT computation that is based on the Pease algorithm, which has the advantage of making the systolic array structure uniform from stage to stage. With slight modifications the algorithm can be directly implemented on a systolic array. The array needs only log2 n processors, where n is the number of inputs words (length of the FFT). It processes data generated at a speed twice the rate of the processor clock.

引用

页码：236 / 239

页数：4

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