A HIGHLY INTEGRATED 40-MIPS (PEAK) 64-B RISC MICROPROCESSOR

A one-million-transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS and 20-MFLOPS peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLB’s) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC RISC architecture, a floating-point unit (FPU) which executes IEEE 754 single- and double-precision floating-point operations, a 6-kilobyte three-way set-associative physical instruction cache, a 2-kilobyte two-way set-associative physical data cache, a memory management unit that has two translation lookaside buffers, and a bus control unit with an ECC circuit. © 1990 IEEE