Elimination of charge-enhancement effects in GaAs FETs with a low-temperature grown GaAs buffer layer

被引：22
|
作者：
McMorrow, D
Weatherford, TR
Curtice, WR
Knudson, AR
Buchner, S
Melinger, JS
Tran, LH
Campbell, AB
机构：
[1] Naval Research Laboratory, Washington
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1995年 / 42卷 / 06期
关键词：
D O I：
10.1109/23.488787
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The use of a low temperature grown GaAs (LT GaAs) buffer layer in GaAs FETs is shown via computer simulation and experimental measurement to reduce ion-induced charge collection by two to three orders of magnitude. This reduction in collected charge is associated with the efficient reduction of charge-enhancement mechanisms in the FETs. Error rate calculations indicate that the soft error rate of LT GaAs integrated circuits will be reduced by several orders of magnitude when compared to conventional FET-based GaAs ICs.
引用
收藏
页码：1837 / 1843
页数：7
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