INDUSTRIAL BIST OF EMBEDDED RAMS

被引：32

作者：

CAMURATI, P ^{[1
]}

PRINETTO, P ^{[1
]}

REORDA, MS ^{[1
]}

BARBAGALLO, S ^{[1
]}

BURRI, A ^{[1
]}

MEDINA, D ^{[1
]}

机构：

[1] POLITECN TORINO, DEPT COMP SCI & AUTOMAT, I-10129 TURIN, ITALY

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1995年 / 12卷 / 03期

关键词：

D O I：

10.1109/MDT.1995.466385

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This built-in self-test scheme for deeply embedded memories implements in hardware test pattern generation algorithm, extending it to word-based memories. Area overhead, performance degradation, additional pins, and test time are minimal. Experimental results confirm high fault coverage for the significant failure modes and full testability of the BIST hardware.

引用

页码：86 / 95

页数：10

共 9 条

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