A SUBMICROMETER MOS-TRANSISTOR IV MODEL FOR CIRCUIT SIMULATION

被引：7

作者：

MASUDA, H

MANO, JI

IKEMATSU, R

SUGIHARA, H

AOKI, Y

机构：

[1] HITACHI MICROCOMP ENGN CO LTD,KODAIRA,JAPAN

[2] HITACHI VLSI ENGN LTD,TOKYO,JAPAN

[3] HITACHI LTD,MUSASHI WORKS,KOKUBUNJI,TOKYO 185,JAPAN

[4] KURUME INST TECHNOL,KURUME,JAPAN

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1991年 / 10卷 / 02期

关键词：

D O I：

10.1109/43.68403

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a submicrometer MOSFET model that is used as a circuit simulator. The object is to realize a simple I-V model that receives good agreement with the experimental result including its geometrical effects. To achieve this, we have developed 1) a novel semi-empirical formula for channel conductance degradation by gate electric field and 2) a compact channel-length modulation model for short channel MOSFET operation in the saturation region. Geometrical effects on the MOSFET model parameters are also studied, focusing on the channel conductance and threshold voltage. Based on experimental verification with CMOS devices fabricated by 0.5-1.3-mu-m technologies, it is concluded that the proposed I-V model and geometrical formulas of the model parameters coincide with the experimental data with the maximum rms error of 1%.

引用

页码：161 / 170

页数：10

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