HARDWARE IMPLEMENTATION OF MONTGOMERY MODULAR MULTIPLICATION ALGORITHM

被引：135
作者：
ELDRIDGE, SE
WALTER, CD
机构：
[1] Computation Department, UMIST, Manchester
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1993年 / 42卷 / 06期
关键词：
DIGITAL ARITHMETIC; FAST COMPUTER ARITHMETIC; MODULAR MULTIPLICATION; PARALLEL BIT OPERATIONS; PUBLIC-KEY CRYPTOGRAPHY; REDUNDANT NUMBER SYSTEMS; RSA ALGORITHM;
D O I：
10.1109/12.277287
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Hardware is described for implementing the fast modular multiplication algorithm of P. L. Montgomery. Comparison with previous techniques shows that his method is up to twice as fast as the best currently available, as well as being more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.
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页码：693 / 699
页数：7
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