REDUCED-COMPLEXITY CIRCUIT FOR NEURAL NETWORKS

被引：1

作者：

WATKINS, SS

CHAU, PM

机构：

[1] UCSD, Department of Electrical and Computer Engineering, CA 92093, La Jolla

来源：

ELECTRONICS LETTERS | 1995年 / 31卷 / 19期

关键词：

NEURAL NETWORKS; REDUCED INSTRUCTION SET COMPUTING;

D O I：

10.1049/el:19951113

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Letter demonstrates that a 10 bit reduced-complexity VLSI circuit can be used in place of a 32 bit floating-point processor to speed up some neural network applications, reducing circuit area and power consumption by 88% with a negligible increase in RMS error. Applications were executed on a radial basis function neurocomputer using the reduced-complexity circuit implemented with FPGA technology. One application produced better results than had been previously obtained for a NASA data set using either neural network or non-neural network approaches.

引用

页码：1644 / 1646

页数：3