An EDA Framework for Reliability Estimation and Optimization of Combinational Circuits

The low reliability of advanced CMOS devices has become a critical issue that can potentially supersede the benefits of the shrinking technology thereby turning design time reliability assessment and optimization a mandatory step in the IC design flow. This paper presents a systematic and integrated methodology to address and improve the combinational circuit reliability measured in terms of Soft Error Rate (SER). First, an algorithm based on probability analysis and logic principles for computing the impact of gate failures on the circuit output is outlined. Then, the proposed SER reduction framework makes use of rewriting based techniques to optimise combinational circuits for reliability. Cut enumeration and Boolean matching driven by reliability aware optimisation algorithm are used to identify best possible replacement candidates. A reliability evaluator has been developed around the open source logic synthesis tool 'abc' to allow integration and evaluation of our method in the context of an IC design flow. Our experiments on a set of MCNC benchmark circuits and 8051 micro controller functional units indicate that the proposed framework can achieve up to 75% reduction of output error probability. On average, about 14% SER reduction is obtained at the expense of very low area overhead of 6.57% that results in 13.52% higher power consumption.