TEMPERATURE-COMPENSATION CIRCUIT TECHNIQUES FOR HIGH-DENSITY CMOS DRAMS

This paper presents novel temperature-compensation circuit techniques for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/degrees-C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/degrees-C. As a result, 6.5-ns faster RAS access time and improved latch-up immunity have been achieved, compared with conventional circuit techniques.