A HARDWARE DESIGN-MODEL FOR CRYPTOGRAPHIC ALGORITHMS

A hardware implementation model is proposed that can be used in the design of stream ciphers, block ciphers and cryptographic hash functions. The cryptographic finite state machine (CFSM) model is no mathematical tool, but a set of criteria that have to be met by a real hardware finite state machine that will be used in the implementation of a cryptographic algorithm. Diffusion is studied by means of the diffusion graph and dependence matrix. For the study of confusion differential cryptanalysis is used. In the paper the design of a high-speed cryptographic coprocessor is presented called Subterranean. This coprocessor can be used for both cryptographic pseudorandom sequence generation and cryptographic hashing. It can be implemented in a straightforward way as (part of) a chip. The small gate-delay allows high clockfrequencies, and even a moderate estimation of 20 MHz leads to a (stream-)encryption speed of 0.3 Gbit/s and hashing speed of 0.6 Gbit/sec.