OPTIMIZATION OF GATE-TO-DRAIN SEPARATION IN SUBMICRON GATE-LENGTH MODULATION-DOPED FETS FOR MAXIMUM POWER GAIN PERFORMANCE

This paper analyzes the effects of the separation between the gate and the drain electrodes on the high-frequency performance limitations of heterostructure MODFET's. Based on the effective gate-length and carrier velocity saturation concepts first the key small-signal equivalent network model parameters of the MODFET are calculated. The concept of open-circuit voltage gain, defined as the transconductance to output conductance ratio (g(m)/g(o)), has been exploited to determine the output conductance with a knowledge of the static electric field and potential at the edge of the gate on the drain side. By treating the c(o)mu(n) product as a function of the gate voltage, the drain current-voltage and transconductance characteristics have been effectively modeled for practical devices. By combining the effects of the intrinsic and parasitic equivalent network parameters this paper has determined the dependence of the g(m)/g(o) ratio, the gate capacitance to the feedback capacitance ratio, the unity current gain frequency (f(tau)) and the maximum frequency of oscillations (f(max) on the gate-to-drain separation (L(gd)). MODFET's based on InAlAs/InGaAs heterostructures lattice-matched to InP substrate with gate-length values of 0.25 mum, 0.15 mum and 0.1 mum are considered for analyses. The optimum values of L(gd) calculated are 600 angstrom, 420 angstrom, and 340 angstrom for the corresponding maximum f(max)-values of 250, 370, and 480 GHz, respectively.