HIGH-SPEED PARALLEL VITERBI DECODING - ALGORITHM AND VLSI-ARCHITECTURE

被引：73

作者：

FETTWEIS, G ^{[1
]}

MEYR, H ^{[1
]}

机构：

[1] RHEIN WESTFAL TH AACHEN, ELECT ENGN, W-5100 AACHEN, GERMANY

来源：

关键词：

D O I：

10.1109/35.79382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

[No abstract available]

引用

页码：46 / 55

页数：10

共 52 条

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