HIGH-SPEED PARALLEL VITERBI DECODING - ALGORITHM AND VLSI-ARCHITECTURE

被引：73

作者：

FETTWEIS, G ^{[1
]}

MEYR, H ^{[1
]}

机构：

[1] RHEIN WESTFAL TH AACHEN, ELECT ENGN, W-5100 AACHEN, GERMANY

来源：

关键词：

D O I：

10.1109/35.79382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

[No abstract available]

引用

页码：46 / 55

页数：10

共 52 条

[1] Bellman Richard, 1962, APPL DYNAMIC PROGRAM
[2] CONTRIBUTIONS TO THE APPLICATION OF THE VITERBI ALGORITHM
BURKHARDT, H
BARBOSA, LC
[J]. IEEE TRANSACTIONS ON INFORMATION THEORY, 1985, 31 (05) : 626 - 634
[3] FANG R, 1986, INT C DIG SAT COMM I, P305
[4] FETTWEIS A, 1976, ELECT COMMUN AEU, V30, P90
[5] FETTWEIS G, 1989, SYSTOLIC ARRAY PROCESSORS, P195
[6] HIGH-RATE VITERBI PROCESSOR - A SYSTOLIC ARRAY SOLUTION
FETTWEIS, G
MEYR, H
[J]. IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1990, 8 (08) : 1520 - 1534
[7] PARALLEL VITERBI ALGORITHM IMPLEMENTATION - BREAKING THE ACS-BOTTLENECK
FETTWEIS, G
[J]. IEEE TRANSACTIONS ON COMMUNICATIONS, 1989, 37 (08) : 785 - 790
[8] FETTWEIS G, 1988, P EUSIPCO 88, V1, P339
[9] FETTWEIS G, 1987, VERFAHREN AUSFURUNG
[10] FETTWEIS G, 1990, APR P ICC ATL, V2, P463