Design of Low Power Parallel Multiplier

Recent trends in the signal processing applications have created a need for energy efficient computation. Multiplication is a major power consuming circuit in many application areas like DSP, cryptography, and communication. This paper presents a novel architecture for the radix-2 Booth recoded multiplier where we remove sign extended bits. The architecture is further optimized using proposed "Booth Recoding Unit" for low power applications. It is done by reducing switching activity on the inputs to the multiplication unit to reduce overall switching activity and hence the dynamic power consumption. We also propose an Adder-Subtractor circuit with reduced switching activity. Test Results show that the proposed design consumes 4 times less power and 15% less area than a conventional radix-2 low power Booth recoded multiplier.