BUILT-IN SELF-TEST DESIGN OF SEMICONDUCTOR MEMORY

被引：0
作者：
RAJASHEKHARA, TN
机构：
[1] Department of Electrical Engineering, State University of New York at Binghamton, Binghamton, NY
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 1991年 / 70卷 / 03期
关键词：
D O I：
10.1080/00207219108921316
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A built-in self-test (BIST) design for semiconductor memory is presented. The design uses up/down counters for linear addressing of memory cells and a transition counter for storing the compressed signature. The test procedure uses marching test patterns and covers stuck-at, transition, and coupling faults.
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页码：645 / 649
页数：5
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